The invention relates to phase-locked loop type clock-signal generators that produce a high-frequency clock signal from a low-frequency clock signal. Among these generators, the invention relates more specifically to those using an oscillator comprising series connected inverters.
A prior art generator 10 of this kind as shown in FIG. 1 includes a frequency divider 12, a phase comparator 14 and an oscillator 16 that are series connected. An output OUT of the oscillator 16 is connected to an input of the frequency divider 12. The loop 10 gives a high-frequency clock signal CKHF (f=FHF) as a function of a reference low-frequency signal CKBF (f=FBF).
The frequency divider 12 receives the clock signal CKHF and gives a signal CKHF_N that is an image of the signal CKHF, and has a frequency equal to f=FHF/N. N is an integer whose value is chosen as a function of the desired frequency FHF0 for the clock signal CKHF, and of the frequency FBF of the reference signal CKBF used: N=FHF0/FBF.
The phase comparator 14 has a positive input and a negative input. The signals CKHF_N and CKBF are respectively applied to these inputs. When the signals CKHF_N and CKBF are equal to 1, the phase comparator 14 determines the phase difference between the signal CKHF_N and CKBF by comparing the relative position of the trailing edges of the clock signal CKHF_N and CKBF. The comparator then produces two logic control signals UP, DOWN as a function of the result of the comparison.
The signals UP, DOWN have the following characteristics. If a trailing edge of CKBF is detected first (instants T1 and T3 in FIGS. 2a to 2d), and the signals CKHF_N and CKBF are previously at a 1, CKBF has a phase lead over CKHF_N. The comparator 14 then gives an active signal UP which, for example, takes the logic value 1. UP is then deactivated on the next trailing edge of the CKHF_N (instants T2 and T4 in FIGS. 2a to 2d).
If a trailing edge of CKHF_N is detected first (instants T5 and T7 in FIGS. 2a to 2d), and the signals CKHF_N and CKBF are previously at a 1, CKBF has a phase delay with respect to CKHF_N. The comparator 14 then gives an active signal DOWN which, for example, takes the logic value 1. DOWN is then deactivated on the next trailing edge of CKBF (instants T6 and T8 in FIGS. 2a to 2d). Otherwise, the signals UP, DOWN remained constant, active or inactive as the case may be.
The oscillator 16 receives the command signals UP, DOWN and, at its output OUT, it gives the clock signal CKHF. Two types of known oscillators used to form a clock signal generator of the kind are shown in FIG. 1. A first type of oscillator, known as an analog oscillator, comprises a voltage generator and a chain of inverters. The voltage generator produces a controlled voltage VC which is a rising voltage if OUT is active, a falling voltage if DOWN is active, and if not, a constant voltage.
The variation xcex94VC of the controlled voltage VC is proportional to the duration of the signals UP, DOWN. In the case of an analog oscillator, the chain of inverters comprises a fixed odd number of series connected identical inverters. A data output of the first inverter is connected to a data input of the last inverter. The chain of inverters produces the clock signal CKHF whose frequency FHF is proportional to the number of inverters in the chain, and to the switching time in the inverters. The switching time of the inverters is itself proportional to the variation xcex94VC of the control voltage given by the voltage generator.
The frequency FHF of the clock signal CKHF obtained thus follows the variations of the controlled voltage and, therefore, those of the control signals UP, DOWN: FHF increases if the signal UP is active, FHF decreases if the signal DOWN is active, FHF is constant if the signals UP, DOWN are inactive.
A second type of oscillator, known as the digital oscillator, comprises an up/down counter and a chain of inverters. The up/down counter produces a control number NR whose value varies as a function of the signals UP, DOWN: NR decreases if the signal UP is active, NR increases if the signal DOWN is active, and NR is constant if the signals UP, DOWN are inactive. The variations xcex94NR of the control number NR are proportional to the duration of the pulses UP, DOWN.
In the case of the digital oscillator, the inverters of the chain of inverters are all identical and, in particular, they have identical propagation times xcex94td. However, the total number ND of inverters in the chain is variable as a function of the control number NR given by the counter. The variations xcex94AND and ND are proportional to the variations of the control number NR.
Since the frequency FHF of the signal CKHF obtained is universally proportional to the number of inverters present in the chain, it varies as a function of the number given by the up/down counter, and therefore, as a function of the signals UP, DOWN as follows: FHF increases if the signal UP is active, FHF decreases if the signal DOWN is active, and FHF is constant if the signals UP, DOWN are inactive.
Thus, regardless of the oscillator chosen, whether analog or digital, the variation xcex94FHF of the frequency FHF generated by a pulse UP, DOWN is proportional to the duration xcex94UP, xcex94DOWN of the signal UP, DOWN applied: xcex94FHF=K*xcex94UP or xcex94AF=K*xcex94DOWN.
The general functioning of the clock signal generator 10 is as follows. If a trailing edge of CKBF is detected first (instants Ti and T3 in FIGS. 2a to 2d), the signals CKHF_N, with CKBF being previously at a 1, CKBF has a phase lead over CKHF_N. It is estimated in this case that the frequency of the CKHF_N is lower than that of CKBF. That is, the frequency of CKHF is lower than the desired value FHF0=N*FBF. The comparator 14 then gives an active signal UP and the frequency FHF of the clock signal CKHF rises. UP is then deactivated on the next trailing edge of CKHF_N (instants Ti and T3 in FIGS. 2a to 2d). The duration of the signal UP applied is thus proportional to the phase difference between CKHF_N and CKBF.
Conversely, if a trailing edge of CKHF_N is detected first (instants T5 and T7 in FIGS. 2a to 2d), with the signals CKHF_N and CKBF being previously at a 1, CKBF has a phase delay with respect to CKHF_N. In this case, it is estimated that the frequency of the CKHF_N is higher than that of CKBF. That is, the frequency of CKHF is higher than the desired value FHF0=N*FBF. The comparator 14 then gives an active signal DOWN and the frequency of the clock signal CKHF decreases. DOWN is then deactivated on the next trailing edge of CKBF (instants T6 and T8 in FIGS. 2a to 2d). The duration of the signal DOWN applied is thus proportional to the phase difference between the signals CKHF_N and CKBF.
When the generator 10 is powered on, the frequency FHF of the signal CKHF is very low. For example, it is equal to the frequency FBF of the reference signal CKBF. The frequency FHF will then vary as a function of the pulses UP, DOWN produced by the phase comparator. It will increase on an average because the pulses UP are more numerous and their duration is greater than that of the pulses DOWN. The frequency FHF will finally converge towards its borderline value FHF0. The variations xcex94FHF of the frequency FHF are a function of the duration xcex94UP, xcex94DOWN, of the pulses UP and DOWN, which is itself proportional to the phase difference between the signals CKHF_N and CKBF. It may be recalled that the frequency of CKFH_N is equal to FHF/N.
The duration of the pulses UP, DOWN is random with respect to the difference in frequency xcex4 between the real frequency FHF of the signal CKHF and the desired frequency FHF0 (xcex4F=FHF=xe2x88x92FHF0). This sometimes leads to an excessively large increase or an excessively large decrease in the frequency FHF. That is, major oscillations of the frequency FHF, especially when this frequency is close to its borderline value FHF0.
For example, if a pulse UP with a large duration is applied (reference numeral 1 in FIGS. 3a to 3d), when the frequency FHF is below its borderline value FHF0 (reference numeral 2 in FIGS. 3a to 3d), then the frequency FHF can increase excessively and become higher than FHF0 (reference numeral 3). In the example, however, another pulse UP appears (reference numeral 4). This pulse UP is due to the difference in phase between the signal CKHF_N (reference numeral 5) and the signal CKBF (reference numeral 6). The frequency FHF is further raised whereas it would have been necessary to lower it.
These oscillations of the frequency FHF may have varying amplitudes and durations. Due to these oscillations, the convergence time of the generator 10, namely the time needed for the frequency FHF to reach its borderline value FHF0, is relatively lengthy.
Since the variation xcex94FHF of the frequency FHF is proportional to the duration xcex94UP, xcex94DOWN of the pulses UP, DOWN, it is possible to choose a small coefficient K of proportionality between the two to limit the amplitude of the oscillations of the frequency FHF.
However, this coefficient K cannot be excessively reduced. Nor can the duration of the pulses UP, DOWN be reduced below a minimum value. Consequently, the phase difference between the signals CKHF_N and CKBF is never completely 0, and the amplitude of the oscillations of FHF cannot be reduced below a minimum value, even after the convergence. Furthermore, if the coefficient of proportionality is too small, the time to obtain the convergence is important.
Should an analog oscillator be used, a filter placed at output of the voltage generator may be used to filter the control voltage, and thus eliminate the variations in the control voltage due to the weakest pulses UP, DOWN. While a filter of this kind is efficient in reducing the amplitude of the oscillations in frequency, especially after the convergence, it takes up a large amount of silicon surface area.
The amplitude and the duration of the oscillations of the frequency FHF, as well as the convergence time, depend especially on the frequency FBF of the reference signal and indirectly on the number N.
The convergence time is in the range of 100 to 500 periods of the reference signal CKBF. If the frequency FBF of the reference signal CKBF is high enough, then the number N is relatively low, in the range of 10 to 50. The oscillations have a low amplitude, and the convergence is fairly rapid and the desired frequency FHF0 is quickly reached. However, if the frequency FBF is relatively low, then the number N is relatively high, in the range of 200, and the oscillations are large and the convergence time soon becomes prohibitive.
Thus, if a very high value of frequency is desired for FHF, for example, in the range of 48 MHZ, then it is necessary to choose a reference signal CKBF with a mean frequency, for example, in the range of 1 MHZ, to make efficient use of the known circuits.
However, it would be useful to be able to use a very low frequency reference signal CKBF, in the range of 10 Hz to 50 kHz, for example, especially for reasons of cost. A reference signal of this kind could be obtained from a particularly stable quartz crystal generator (FBF in the range of 32 kHz) or else from a national electrical power system, which has a signal frequency of 50 Hz, for example, that is also stable. Other sources of low-frequency and low-cost reference signals may also be considered.
In view of the foregoing background, an object of the invention is to provide a phase-locked loop type of clock signal generator wherein the convergence time is reduced as compared with that of known circuits.
Another object of the invention is to provide a clock signal generator that uses very low frequency reference signals to obtain very high frequency clock signals.
These and other objects, advantages and features according to the invention are provided by an integrated circuit comprising a generator for producing a clock signal from a reference signal, with the generator comprising a frequency divider to give a low-frequency signal that is an image of the clock signal, and a comparator to compare the phase of the low-frequency signal with that of the reference signal and give a control signal as a function of the result of the comparison.
The generator further includes an oscillator, to produce the high-frequency signal (CKHF) from the control signal, and a reset circuit to give a reset signal at each leading edge of the reference signal to synchronize the low-frequency signal with the reference signal.
The integrated circuit further comprises an oscillator driving means to modulate a value of a coefficient of proportionality as a function of the result of the comparison. A variation of the frequency of the high-frequency signal is equal to the duration of the control signal multiplied by the coefficient of proportionality.
The idea of the invention thus is to use a reset circuit to synchronize the low-frequency signal (the image of the high frequency signal) with the reference signal. After synchronization, the relative phase difference detected by the phase comparator between the trailing edges of the low-frequency signal and those of the reference signal is then directly proportional to the frequency difference between these two signals.
The duration of the control signal produced by the comparator is therefore directly proportional to the difference between the real frequency FHF of the clock signal and its desired borderline value FHF0. The duration of the control signal is therefore always large if the difference between FHF and FHF0 is large. Conversely, the duration of the control signal is always small when the difference between FHF and FHF0 is small. It is thus far easier to manage the variations in the frequency FHF of the clock signal.
The variations in the frequency FHF are restricted with the invention. This feature accordingly limits the risks of going beyond the desired borderline value of FHF0 by excessively raising (or, as the case may be, excessively lowering) the frequency FHF by the application of an excessively lengthy control signal. Consequently, the phenomenon presented above (FIGS. 3a to 3d) is eliminated. The oscillations of the high-frequency signal are greatly reduced, and the number of active pulses of the control signal is also limited, and the convergence time is consequently reduced. It is no longer necessary to filter the signals.
The reset signal is used to synchronize the low-frequency signal with the reference signal by resetting the frequency divider. The reset signal, as the case may be, may be applied additionally to an input of the comparator to deactivate the control signal at each leading edge of the reference signal.
According to one embodiment, the reset circuit comprises a first flip-flop circuit having a data input to which the reference signal is applied, a clock input to which the clock signal is applied, and a data output. A first logic gate comprises two inputs respectively connected to the data input and to the data output of the first flip-flop circuit, and an output at which the reset signal is given. The reset signal is thus activated on a leading edge of the reference signal and deactivated on a leading edge of the clock signal.
According to one embodiment, the divider comprises a counter to count pulses of the high-frequency signal and give a stop signal when the number of pulses counted reaches the desired number N/2. A second flip-flop circuit has a clock input to which the stop signal is applied, and a negative data output connected to a data input of the second flip-flop circuit. The second flip-flop circuit provides the low-frequency signal at its negative output. A second logic gate has two inputs to which there are respectively applied the stop signal by an inverter and the reset signal. The second logic signal produces a setting signal at an output connected to a setting input of the counter. The setting signal is active when the stop signal is active or when the reset signal is active.